The PCI Express standard stagnated after the release of PCI Express 3.0 in 2010. Major speed improvements are coming to PCI Express in the near future.
The PCI Special Interest Group (PCI-SIG) published PCI Express 5.0 this week, bringing faster speeds to connected devices including solid-state drives (SSDs) and network interface cards (NICs)—at least, in theory. While there is every reason to believe PCIe 5.0 will enjoy widespread adoption in the future, getting there will take significant engineering effort.
At Computex 2019 in Taiwan, AMD announced their widely anticipated third-generation Ryzen platform, beating Intel in bringing support for PCIe 4.0. Storage vendors have started showing off PCIe 4.0-compatible SSDs as well, with these parts expected to start shipping in July. AMD is actually not the first, as IBM's POWER9 processor supports PCIe 4.0, though for desktop users, this has only been available in Raptor Computing's Talos and Blackbird systems.
On its own merits, PCIe 5.0 is impressive, doubling the transfer rates from PCIe 4.0, which in turn doubled transfer rates from PCIe 3.0. In terms of practical deployments, a PCIe 5.0 x1 slot delivers the same bandwidth (~4GB/s) as a full-size, first-generation PCIe x16 slot from 2003, commonly used in graphics cards.
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In terms of practical deployment, it is likely to be some time before PCIe 5.0 devices arrive, though it is possible that Intel may skip PCIe 4.0 entirely, as their Compute Express Link (CXL) technology for connecting FPGA-based accelerators is based on PCIe 5.0. This should be taken with a grain of salt—rumors indicated that Intel planned to skip a 10nm manufacturing process, in favor of moving to 7nm, following low yields on 10nm parts. Intel's Computex announcements show 10nm plans for mobile systems, though desktop-class CPUs have yet to be announced.
From an implementation standpoint, the technical complexity between 4.0 and 5.0 is lower than 3.0 and 4.0, making it likely to see a quick upgrade for existing 4.0 designs.
The first PCIe 5.0 parts may be seen in very late 2020, though 2021 is a more likely pace, based on comments from industry executives.
"With the jump to 32Gbps signaling, the PCI Express 5.0 specification is bringing new levels of performance for demanding applications in the HPC, Cloud Computing, AI, and Networking and Storage spaces," Stephane Hauradou, CTO of PLDA, noted in a press release. "PLDA interface IP for the PCIe 5.0 specification are available today and are already being integrated into SoCs due for tape-out in early 2020."
The PCI-SIG annual conference is next month, which should clarify vendor roadmaps for the debut of PCIe 5.0-compatible products.
For more, check out "Tracking 5G: Ookla's coverage map tracks worldwide network rollout" and "Vulnerabilities in industrial control systems surface lack of basic security hygiene" on TechRepublic.
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